SI5040-D-GM【PDF 22/108 页】IC TXRX XFP 10GBPS 32LGA

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Si5040

LOS=1?

Y

Y

LOLonLOS =0 and

ltrOnLos=0? (Default)

LOLonLOS =1

and ltrOnLos =0?

LOLonLOS = 0

and ltrOnLos = 1?

LOLonLOS = 1

and ltrOnLos = 1?

Y

CDR continuously tries to lock to

incoming data, and the VCO

frequency does not get re-centered

prior to the lock acquisition

process.

Y

Next Figure

VCOCAL[1:0] = 01?

VCOCAL[1:0] = 00?

VCOCAL[1:0] = 10

(Default)?

VCOCAL[1:0] = 11?

Y

Y

The internal VCO pull

Y

Y

Is refClk

present?

Y

range will be automatically

re-centered to the

reference clock frequency

Y

Is refClk

present?

to start the CDR lock

N

acquisition process.

N

The entire VCO frequency

range will be swiped to start the

CDR lock acquisition process.

VCO stays at the center of its

frequency range awaiting for

refClk.

Invalid mode!

LOL will stay on.

Figure 12. CDR and VCO Behaviors Upon Declaring LOS (1 of 2)

LOLonLOS = 0 and

ltrOnLos = 1?

Y

From Previous Figure

Since ltr has been set to 1

prior to the assertion of

LOLonLOS =1 and

ltrOnLos =1?

Y

Ltr (bit 1 in Register 7)= 1?

Y

LOS, CMU maintains lock

to the reference and the

CDR lock acquisition

VCOCAL[1:0] = X1?

VCOCAL[1:0] = X0?

depends on CDRLTDATA

N

control in Register 7.

Y

Y

Is refClk

present?

N

Y

CMU locks to the

reference clock until

LOS is clear. Note that

LOL will be off during

this period.

Invalid mode!

ltrOnLOS is enabled

but refClk is disabled.

Y

Is refClk

present?

N

VCO stays at the

center of its

frequency range

awaiting for refClk.

The internal VCO pull range

will be automatically re-

centered to the reference

clock frequency to start the

VCO stays at the center of

its frequency range awaiting

for refClk.

CDR lock acquisition

process. Note that LOL will

not be cleared.

Figure 13. CDR and VCO Behaviors Upon Declaring LOS (2 of 2)

22

Rev. 1.3

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